SEMICONDUCTOR MEMORY DEVICE

According to an embodiment, a semiconductor memory device includes first and second groups each including a plurality of memory cells, and a control circuit. The control circuit is configured to successively apply a first voltage and a second voltage which is higher than the first voltage to a memory cell in the first or second group, and to apply a third voltage to the memory cell after applying the second voltage. When the memory cell is included in the first group, the control circuit applies the third voltage to the memory cell a time earlier with respect to a time when the second voltage is applied than when the memory cell is included in the second group. Each of the first and second groups corresponds to a data erase unit or a unit larger than the data erase unit.