SEMICONDUCTOR APPARATUS

A semiconductor apparatus including: a peripheral circuit region and a memory region including a plurality of unit memory blocks coupled to the peripheral circuit region through data lines and control signal lines. The control signal lines having a path configuration configured to equalize a value corresponding to a difference between times required for transferring data from the peripheral circuit region to the plurality of unit memory blocks with another value corresponding to a difference between times required for transferring control signals related to data input/output from the peripheral circuit region to the plurality of unit memory blocks to substantially a same value.