Porous Cu on Cu Surface for Semiconductor Packages

A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a therm...

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Bibliographische Detailangaben
Hauptverfasser:	Lee, Swee Kah, Seah, Siew Ching, Muhammat Sanusi, Muhammad, Pielmeier, Norbert, Napetschnig, Evelyn, Lai, Chin Yung, Othman, Nurfarena
Format:	Patent
Sprache:	eng
Schlagworte:	APPARATUS THEREFOR BASIC ELECTRIC ELEMENTS CHEMISTRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROFORMING ELECTROLYTIC OR ELECTROPHORETIC PROCESSES METALLURGY PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTIONOF COATINGS SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 μm to 10 μm. A method of manufacturing a metal surface with such micropores also is described.