IC layout design method

Disclosed is an IC layout design method capable of improving the result of an IC layout design process including a front-end process and a back-end process. The IC layout design method includes the following steps: executing the front-end process according to initial clock latency setting and thereby generating an initial netlist; executing at least a part of the back-end process according to the initial netlist and thereby obtaining updated clock latency setting; executing at least a part of the front-end process according to the updated clock latency setting and thereby generating an updated netlist; and executing the back-end process according to the updated netlist and thereby obtaining the result of the IC layout design process.