HIGH DENSITY FRACTIONAL BIT SOLID STATE DRIVES USING CODED SET PARTITIONS

Fractional bit storage is disclosed herein which allows for storage of additional bits distributed over multiple SSD cells and maximizes data stored for SSD cells with non-binary amounts of allowable threshold voltages while minimizing required bits dedicated to error correction code (ECC). For an SSD cell with twenty-four levels of threshold voltage, set partitioning is used to create three equal subsets of levels each corresponding to eight levels of threshold voltage and each partitioned subset able to encode three bits. Each partitioned subset is designed with eight allowable threshold voltage ranges, each of which is separated from any other allowable threshold voltage range by at least two of the twenty-four levels of maximum threshold voltage. By choosing both set partitioning and assigning bit values determined via code modulation, bits stored within a partitioned subset are protected without the need for additional ECC.