3D NAND STRUCTURES WITH DECREASED PITCH

3D NAND STRUCTURES WITH DECREASED PITCH

Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments fo...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Kwon, Thomas, Han, Xinhai
Format: Patent
Sprache:eng
Schlagworte:
ELECTRICITY
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Beschreibung
Zusammenfassung:Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.