SHIFT-FOLDING FOR EFFICIENT LOAD COALESCING IN A BINARY TRANSLATION BASED PROCESSOR
A processor includes an instruction fetch circuit to retrieve instructions from memory, and a decode unit circuit to decode retrieved instructions. The decode unit circuit identifies a shift instruction, accumulates a shift folded immediate value to track a number of bit positions shifted for a sour...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A processor includes an instruction fetch circuit to retrieve instructions from memory, and a decode unit circuit to decode retrieved instructions. The decode unit circuit identifies a shift instruction, accumulates a shift folded immediate value to track a number of bit positions shifted for a source register, and prevents the shift instruction from allocation to an execution unit of the processor. |
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