METHODS OF FABRICATING SEMICONDUCTOR PACKAGE

Disclosed is a method of fabricating a semiconductor package, the method including sawing a portion of the thickness of a substrate downward from an upper surface of the substrate along a boundary region between individual chips to form a sawing groove; forming a resin material on the sawing groove...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Lee, Jin Kuk, Kwon, Jae Jin
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:Disclosed is a method of fabricating a semiconductor package, the method including sawing a portion of the thickness of a substrate downward from an upper surface of the substrate along a boundary region between individual chips to form a sawing groove; forming a resin material on the sawing groove and the substrate; removing portions of the resin material to form post spaces on the substrate; filling a conductive material into the post spaces to form posts; respectively forming redistribution layers on the posts; respectively forming insulating film patterns or under bump metal (UBM) patterns on the redistribution layers; respectively bonding solder balls onto the redistribution layers or the UBM patterns; and sawing the resin material to separate into individual chips.