STANDARD CELL HAVING MIXED FLIP-WELL AND CONVENTIONAL WELL TRANSISTORS

An LVT-RVT cell includes an LVT PMOS transistor adjacent to an RVT NMOS transistor, whereby the LVT and RVT transistors are placed inside a common p-well and are biased using the same voltage potential. The cell thus employs a flipped well for the PMOS transistor and a conventional (unflipped) well for the NMOS transistor. By arranging the LVT-RVT cell in this way, the cell can function at lower voltages, thereby conserving power, while also improving the performance of the composite function. Furthermore, the LVT-RVT cell can be placed adjacent to RVT cells to further reduce power consumption and improve performance of the RVT cells within the block.