APPARATUSES AND METHODS FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY

Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.