SUB-SAMPLED COLOR CHANNEL READOUT WIRING FOR VERTICAL DETECTOR PIXEL SENSORS

In an array containing rows and columns of multi-color vertical detector color pixel sensors disposed in a rows and columns of the array, a readout wiring architecture includes a plurality of row-select lines for each row of the array, equal to the number of colors in the vertical detector color pixel sensors, an individual column line for each column, a transfer transistor for each individual color detector coupled between a color detector and a column line associated with the column in which the color detector is disposed. Each transfer transistor has a gate coupled to one of the plurality of row-select lines in a row in which the vertical detector color pixel sensor is disposed. The gates of at least some of the transfer transistors in each row for each color detector in adjacent columns of the array are coupled to different ones of the row-select lines for that row.