LOW-POWER, LOW-LATENCY TIME-TO-DIGITAL-CONVERTER-BASED SERIAL LINK

A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into...

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Bibliographische Detailangaben
Hauptverfasser:	Hailu, Eskinder, Pandita, Bupesh, Jun, Yong Suk, Zhu, Zhi, Chen, Minhan, Goudarzi, Hadi, Boyette, Jon
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY HOROLOGY PHYSICS PULSE TECHNIQUE TIME-INTERVAL MEASURING TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.