BYPASS PATH LOSS REDUCTION
Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one in...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Lee, Junhyung Agarwal, Bipul Lee, Yong Hee Heo, Junwon |
| description | Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2020099410A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2020099410A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2020099410A13</originalsourceid><addsrcrecordid>eNrjZJByigxwDA5WCHAM8VDw8QeyglxdQp1DPP39eBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRgYGlpYmhgaOhMXGqALlsITg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>BYPASS PATH LOSS REDUCTION</title><source>esp@cenet</source><creator>Lee, Junhyung ; Agarwal, Bipul ; Lee, Yong Hee ; Heo, Junwon</creator><creatorcontrib>Lee, Junhyung ; Agarwal, Bipul ; Lee, Yong Hee ; Heo, Junwon</creatorcontrib><description>Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200326&DB=EPODOC&CC=US&NR=2020099410A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200326&DB=EPODOC&CC=US&NR=2020099410A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lee, Junhyung</creatorcontrib><creatorcontrib>Agarwal, Bipul</creatorcontrib><creatorcontrib>Lee, Yong Hee</creatorcontrib><creatorcontrib>Heo, Junwon</creatorcontrib><title>BYPASS PATH LOSS REDUCTION</title><description>Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJByigxwDA5WCHAM8VDw8QeyglxdQp1DPP39eBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRgYGlpYmhgaOhMXGqALlsITg</recordid><startdate>20200326</startdate><enddate>20200326</enddate><creator>Lee, Junhyung</creator><creator>Agarwal, Bipul</creator><creator>Lee, Yong Hee</creator><creator>Heo, Junwon</creator><scope>EVB</scope></search><sort><creationdate>20200326</creationdate><title>BYPASS PATH LOSS REDUCTION</title><author>Lee, Junhyung ; Agarwal, Bipul ; Lee, Yong Hee ; Heo, Junwon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020099410A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee, Junhyung</creatorcontrib><creatorcontrib>Agarwal, Bipul</creatorcontrib><creatorcontrib>Lee, Yong Hee</creatorcontrib><creatorcontrib>Heo, Junwon</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, Junhyung</au><au>Agarwal, Bipul</au><au>Lee, Yong Hee</au><au>Heo, Junwon</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BYPASS PATH LOSS REDUCTION</title><date>2020-03-26</date><risdate>2020</risdate><abstract>Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2020099410A1 |
| source | esp@cenet |
| subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION |
| title | BYPASS PATH LOSS REDUCTION |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T17%3A58%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lee,%20Junhyung&rft.date=2020-03-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2020099410A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |