MEMORY DEVICE AND OPERATING METHOD THEREOF

The present disclosure relates to a memory device including a BIST circuit and an operating method thereof. The memory device includes a comparison circuit comparing test pattern data with sensing data to generate a comparison signal, a status information generating circuit generating a fail mask signal by marking data in which a failure occurs in the sensing data in response to the comparison signal, a column address generating circuit generating column addresses sequentially increasing in response to an input/output strobe signal, a latch enable signal generating circuit generating a latch enable signal in response to the fail mask signal, and an input/output circuit receiving the column addresses and selectively latching a column address in which a failure occurs among the column addresses in response to the latch enable signal.