WAFER LEVEL PACKAGING WITH INTEGRATED ANTENNA STRUCTURES

WAFER LEVEL PACKAGING WITH INTEGRATED ANTENNA STRUCTURES

RF semiconductor chips may be packaged on wafer level on the basis of a two-step process for providing a package material, thereby providing very short electrical connections between antenna structures formed in the package material and the semiconductor chip. In some illustrative embodiments, the a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Goetze, Christian, Wieland, Marcel
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:RF semiconductor chips may be packaged on wafer level on the basis of a two-step process for providing a package material, thereby providing very short electrical connections between antenna structures formed in the package material and the semiconductor chip. In some illustrative embodiments, the antenna structures may be provided above the semiconductor chip, which results in a very space-efficient overall configuration.