WAFER-LEVEL PACKAGING METHOD AND PACKAGE STRUCTURE THEREOF

A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.