DISPLAY DEVICE

Regarding any gate clock signal transmission line, assuming that two signal transmission lines that are adjacent to the focused gate clock signal transmission line are defined as a first adjacent signal line and a second adjacent signal line, and that a combination of a potential of the first adjacent signal line and a potential of the second adjacent signal line when a potential of the focused gate clock signal transmission line changes from a high level to a low level is defined as an adjacent signal line state, a plurality of signal transmission lines including the plurality of gate clock signal transmission lines are disposed between the signal input terminal and the gate driver so that the adjacent signal line state for all of the plurality of gate clock signal transmission lines are the same.