CLIENT LATENCY-AWARE MICRO-IDLE MEMORY POWER MANAGEMENT

Systems and methods are disclosed for providing micro-idle memory power management. One embodiment of a method comprises receiving and storing an exit latency vote from each of a plurality of memory subsystems on a system on chip electrically coupled to a system memory. In response to a micro-idle memory state in which each of the memory subsystems are idle, a minimum exit latency value from the plurality of exit latency votes is determined. One of a plurality of system memory modes is selected which has a micro-idle sleep time that meets the minimum exit latency value while minimizing system memory power consumption. The selected system memory mode is initiated.