FLEXIBLE AND IN-LINE REGISTER COMPARISON FOR BUG ANALYSIS

FLEXIBLE AND IN-LINE REGISTER COMPARISON FOR BUG ANALYSIS

A validation and testing method is provided. The validation and testing method is executable by a processor coupled to a memory. The validation and testing method includes inserting intermediary save points within an instruction stream. The method includes executing the instruction stream including...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Duale, Ali Y, Wittig, Dennis
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A validation and testing method is provided. The validation and testing method is executable by a processor coupled to a memory. The validation and testing method includes inserting intermediary save points within an instruction stream. The method includes executing the instruction stream including the intermediary save points. The method includes executing a save operation for data in one or more registers at each of the one or more intermediary save points.