Sampling Phase-Locked Loop (PLL)

An apparatus is disclosed that implements a sampling phase-locked loop. In an example aspect, the apparatus includes a phase frequency detector, a relative phase signal determiner, a voltage-controlled oscillator (VCO), and a feedback path. The phase frequency detector is configured to produce a phase indication signal based on a reference signal and a feedback signal. The relative phase signal determiner is coupled to the phase frequency detector and includes a sampler. The relative phase signal determiner is configured to determine a relative phase signal based on the phase indication signal using the sampler. The VCO is coupled to the relative phase signal determiner and is configured to produce an oscillating signal based on the relative phase signal. The feedback path is disposed between the VCO and the phase frequency detector. The feedback path is configured to provide the feedback signal to the phase frequency detector using the oscillating signal.