STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the seco...

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Hauptverfasser:	SCHAEFER, Andre, VOGT, Pete D, HALBERT, John B, MORROW, Warren, KIM, Jin, SHOEMAKER, Kenneth D
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
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creator	SCHAEFER, Andre VOGT, Pete D HALBERT, John B MORROW, Warren KIM, Jin SHOEMAKER, Kenneth D
description	A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.
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The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAJDnF09nZ1UfB19fUPilQI9wzxUPD0C3ENcnN0dlUICPIP83Tx9HNX8HdzC3YNgUg5-_v5uTqHBPMwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDQ0tjAxNLU2NHQ2PiVAEA0Qcq3A</recordid><startdate>20191003</startdate><enddate>20191003</enddate><creator>SCHAEFER, Andre</creator><creator>VOGT, Pete D</creator><creator>HALBERT, John B</creator><creator>MORROW, Warren</creator><creator>KIM, Jin</creator><creator>SHOEMAKER, Kenneth D</creator><scope>EVB</scope></search><sort><creationdate>20191003</creationdate><title>STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS</title><author>SCHAEFER, Andre ; VOGT, Pete D ; HALBERT, John B ; MORROW, Warren ; KIM, Jin ; SHOEMAKER, Kenneth D</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019304953A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>SCHAEFER, Andre</creatorcontrib><creatorcontrib>VOGT, Pete D</creatorcontrib><creatorcontrib>HALBERT, John B</creatorcontrib><creatorcontrib>MORROW, Warren</creatorcontrib><creatorcontrib>KIM, Jin</creatorcontrib><creatorcontrib>SHOEMAKER, Kenneth D</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SCHAEFER, Andre</au><au>VOGT, Pete D</au><au>HALBERT, John B</au><au>MORROW, Warren</au><au>KIM, Jin</au><au>SHOEMAKER, Kenneth D</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS</title><date>2019-10-03</date><risdate>2019</risdate><abstract>A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
title	STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
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