CO-PLACEMENT OF RESISTOR AND OTHER DEVICES TO IMPROVE AREA & PERFORMANCE

Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel metal vias coupling the BEOL resistor layer to one or more metal...

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Bibliographische Detailangaben
Hauptverfasser: WEE, Tin Tin, SCHNEIDER, Jacob, LOKE, Alvin Leng Sun
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel metal vias coupling the BEOL resistor layer to one or more metal layers underneath the BEOL resistor layer, and a diode residing on a silicon substrate underneath the one or more metal layers, wherein a planar surface of the diode and a planar surface of the resistor at least partially overlap with each other, and the diode and the resistor are coupled to each other through the plurality of interlevel metal vias.