Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cost Package

A method to fabricate a land grid array wafer level chip scale package is described. A plurality of silicon dies are provided on a wafer. Openings are etched through a dielectric layer to metal pads on the silicon dies. At least one redistribution layer is formed over the dielectric layer and contacting at least one metal pad. A second dielectric layer is deposited on the at least one redistribution layer. An opening is etched through the second dielectric layer to the at least one redistribution layer and a landing pad is formed on the redistribution layer in the opening. The landing pad may be a portion of the redistribution layer exposed by the opening. Alternatively, the landing pad may be an under bump metal (UBM) layer deposited on the exposed redistribution layer and patterned. The landing pad is covered with an oxidation preventing layer.