SYSTEM AND METHOD OF REDUCING COMPUTER PROCESSOR POWER CONSUMPTION USING MICRO-BTB VERIFIED EDGE FEATURE

SYSTEM AND METHOD OF REDUCING COMPUTER PROCESSOR POWER CONSUMPTION USING MICRO-BTB VERIFIED EDGE FEATURE

According to one general aspect, an apparatus may include a front end logic section comprising a main-branch target buffer (BTB). The apparatus may also include a micro-BTB separate from the main BTB, and configured to produce prediction information associated with a branching instruction and mark p...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: ZURASKI, Jr., Gerald David, SUNDARAM, Karthik, DUNDAS, James David
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:According to one general aspect, an apparatus may include a front end logic section comprising a main-branch target buffer (BTB). The apparatus may also include a micro-BTB separate from the main BTB, and configured to produce prediction information associated with a branching instruction and mark prediction information as verified when one or more conditions are satisfied. Wherein the front end logic section is configured to be, at least partially, powered down when the data stored by the micro-BTB that results in the prediction information is marked as previously verified.