Configurable bus

A device includes an analog block array, a first analog bus segment coupled to the analog block array, a second analog bus segment coupled to the analog block array, and a third analog bus segment coupled to the analog block array. The device also includes a first I/O pin selectively couplable to th...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kutz, Harold M, Williams, Timothy John, Thiagarajan, Eashwar, Snyder, Warren S
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A device includes an analog block array, a first analog bus segment coupled to the analog block array, a second analog bus segment coupled to the analog block array, and a third analog bus segment coupled to the analog block array. The device also includes a first I/O pin selectively couplable to the first analog bus segment, a second I/O pin selectively couplable to the second analog bus segment, and a third I/O pin selectively couplable to the third analog bus segment. A first switch is configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment, and a second switch is configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment. In a first mode of operation, the first and second switches are open. In a second mode of operation, the first switch is closed. In a third mode of operation, the second switch is closed.