ELECTROSTATIC DISCHARGE CLAMP WITH REDUCED OFF-STATE POWER CONSUMPTION

ELECTROSTATIC DISCHARGE CLAMP WITH REDUCED OFF-STATE POWER CONSUMPTION

The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Poro, III, Richard A, GINAWI, Ahmed Y, Stricker, Andreas D, Loiseau, Alain F, Lukaitis, Joseph M, Gebreselasie, Ephrem G
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
GENERATION
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.