FINE DELAY STRUCTURE WITH PROGRAMMABLE DELAY RANGES

FINE DELAY STRUCTURE WITH PROGRAMMABLE DELAY RANGES

A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Yuan, Xiaobin, Tran, Hung H, Prasad, Mangal, Tiner, Marshall D
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.