IGBT with Fully Depletable n- and p-Channel Regions

A power semiconductor device has a semiconductor body coupled to first and second load terminal structures, the semiconductor body configured to conduct a load current during a conducting state of the device and having a drift region. The power semiconductor device includes a plurality of cells, each cell having: a first mesa in a first cell portion, the first mesa including: a first port region, and a first channel region, the first mesa exhibiting a total extension of less than 100 nm in a lateral direction, and a second mesa in a second cell portion including: a second port region, and a second channel region. A trench structure includes a control electrode structure configured to control the load current by inversion or accumulation. A guidance zone of the second conductivity type is below the second channel region and is displaced from the first and the second channel regions.