FORMING STACKED TWIN III-V NANO-SHEETS USING ASPECT-RATIO TRAPPING TECHNIQUES

FORMING STACKED TWIN III-V NANO-SHEETS USING ASPECT-RATIO TRAPPING TECHNIQUES

A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating diele...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BALAKRISHNAN, Karthik, REZNICEK, Alexander, HASHEMI, Pouya, KHOJASTEH, Mahmoud
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating dielectric.