MICROCONTROLLER INSTRUCTION MEMORY ARCHITECTURE FOR NON-VOLATILE MEMORY

An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.