REFERENCE VOLTAGE STABILIZING CIRCUIT AND INTEGRATED CIRCUIT PROVIDED WITH SAME

A transistor (M1) whose gate is capacitance-coupled to a wiring (L1) is connected between the wirings (L1, L2) connected to output nodes (OT1, OT2) outputting a reference voltage (VREF_OUT). A replica circuit (20) having a resistor (22) and a transistor (M2) connected in series is provided between t...

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Hauptverfasser: NOMASAKI, Daisuke, MORIE, Takashi
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creator NOMASAKI, Daisuke
MORIE, Takashi
description A transistor (M1) whose gate is capacitance-coupled to a wiring (L1) is connected between the wirings (L1, L2) connected to output nodes (OT1, OT2) outputting a reference voltage (VREF_OUT). A replica circuit (20) having a resistor (22) and a transistor (M2) connected in series is provided between the wirings (L1, L2). Gates of the transistors (M1, M2) are connected to each other. A differential amplifier (23) receives a voltage (V_RP) of a node (N1) between the resistor (22) and the transistor (M1) and a standard voltage (V_ID), and provides an output to the gate of the transistor (M2).
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2019068213A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2019068213A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2019068213A13</originalsourceid><addsrcrecordid>eNrjZPAPcnVzDXL1c3ZVCPP3CXF0d1UIDnF08vTxjPL0c1dw9gxyDvUMUXD0c1Hw9AtxdQ9yDHF1gQsHBPmHeboABcI9QzwUgh19XXkYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBoaWBmYWRobGjoTFxqgAOri_K</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>REFERENCE VOLTAGE STABILIZING CIRCUIT AND INTEGRATED CIRCUIT PROVIDED WITH SAME</title><source>esp@cenet</source><creator>NOMASAKI, Daisuke ; MORIE, Takashi</creator><creatorcontrib>NOMASAKI, Daisuke ; MORIE, Takashi</creatorcontrib><description>A transistor (M1) whose gate is capacitance-coupled to a wiring (L1) is connected between the wirings (L1, L2) connected to output nodes (OT1, OT2) outputting a reference voltage (VREF_OUT). A replica circuit (20) having a resistor (22) and a transistor (M2) connected in series is provided between the wirings (L1, L2). Gates of the transistors (M1, M2) are connected to each other. A differential amplifier (23) receives a voltage (V_RP) of a node (N1) between the resistor (22) and the transistor (M1) and a standard voltage (V_ID), and provides an output to the gate of the transistor (M2).</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CODE CONVERSION IN GENERAL ; CODING ; CONTROLLING ; DECODING ; ELECTRICITY ; PHYSICS ; REGULATING ; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190228&amp;DB=EPODOC&amp;CC=US&amp;NR=2019068213A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190228&amp;DB=EPODOC&amp;CC=US&amp;NR=2019068213A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NOMASAKI, Daisuke</creatorcontrib><creatorcontrib>MORIE, Takashi</creatorcontrib><title>REFERENCE VOLTAGE STABILIZING CIRCUIT AND INTEGRATED CIRCUIT PROVIDED WITH SAME</title><description>A transistor (M1) whose gate is capacitance-coupled to a wiring (L1) is connected between the wirings (L1, L2) connected to output nodes (OT1, OT2) outputting a reference voltage (VREF_OUT). A replica circuit (20) having a resistor (22) and a transistor (M2) connected in series is provided between the wirings (L1, L2). Gates of the transistors (M1, M2) are connected to each other. A differential amplifier (23) receives a voltage (V_RP) of a node (N1) between the resistor (22) and the transistor (M1) and a standard voltage (V_ID), and provides an output to the gate of the transistor (M2).</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>CONTROLLING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>REGULATING</subject><subject>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAPcnVzDXL1c3ZVCPP3CXF0d1UIDnF08vTxjPL0c1dw9gxyDvUMUXD0c1Hw9AtxdQ9yDHF1gQsHBPmHeboABcI9QzwUgh19XXkYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBoaWBmYWRobGjoTFxqgAOri_K</recordid><startdate>20190228</startdate><enddate>20190228</enddate><creator>NOMASAKI, Daisuke</creator><creator>MORIE, Takashi</creator><scope>EVB</scope></search><sort><creationdate>20190228</creationdate><title>REFERENCE VOLTAGE STABILIZING CIRCUIT AND INTEGRATED CIRCUIT PROVIDED WITH SAME</title><author>NOMASAKI, Daisuke ; MORIE, Takashi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019068213A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>CONTROLLING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>REGULATING</topic><topic>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</topic><toplevel>online_resources</toplevel><creatorcontrib>NOMASAKI, Daisuke</creatorcontrib><creatorcontrib>MORIE, Takashi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NOMASAKI, Daisuke</au><au>MORIE, Takashi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>REFERENCE VOLTAGE STABILIZING CIRCUIT AND INTEGRATED CIRCUIT PROVIDED WITH SAME</title><date>2019-02-28</date><risdate>2019</risdate><abstract>A transistor (M1) whose gate is capacitance-coupled to a wiring (L1) is connected between the wirings (L1, L2) connected to output nodes (OT1, OT2) outputting a reference voltage (VREF_OUT). A replica circuit (20) having a resistor (22) and a transistor (M2) connected in series is provided between the wirings (L1, L2). Gates of the transistors (M1, M2) are connected to each other. A differential amplifier (23) receives a voltage (V_RP) of a node (N1) between the resistor (22) and the transistor (M1) and a standard voltage (V_ID), and provides an output to the gate of the transistor (M2).</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
CONTROLLING
DECODING
ELECTRICITY
PHYSICS
REGULATING
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
title REFERENCE VOLTAGE STABILIZING CIRCUIT AND INTEGRATED CIRCUIT PROVIDED WITH SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T23%3A53%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NOMASAKI,%20Daisuke&rft.date=2019-02-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2019068213A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true