MEMORY DEVICES WITH READ LEVEL CALIBRATION
Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to...
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creator | Alsasua, Gianni S Fei, Peng Miller, Michael G Singidi, Harish R Padilla, Renato C Besinga, Gary F Awusie, Roland J Hoei, Jung Sheng Muchherla, Kishore Kumar |
description | Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller. |
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In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190207&DB=EPODOC&CC=US&NR=2019043592A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190207&DB=EPODOC&CC=US&NR=2019043592A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Alsasua, Gianni S</creatorcontrib><creatorcontrib>Fei, Peng</creatorcontrib><creatorcontrib>Miller, Michael G</creatorcontrib><creatorcontrib>Singidi, Harish R</creatorcontrib><creatorcontrib>Padilla, Renato C</creatorcontrib><creatorcontrib>Besinga, Gary F</creatorcontrib><creatorcontrib>Awusie, Roland J</creatorcontrib><creatorcontrib>Hoei, Jung Sheng</creatorcontrib><creatorcontrib>Muchherla, Kishore Kumar</creatorcontrib><title>MEMORY DEVICES WITH READ LEVEL CALIBRATION</title><description>Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDydfX1D4pUcHEN83R2DVYI9wzxUAhydXRR8HENc_VRcHb08XQKcgzx9PfjYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBoaWBibGppZGjobGxKkCANiTJX8</recordid><startdate>20190207</startdate><enddate>20190207</enddate><creator>Alsasua, Gianni S</creator><creator>Fei, Peng</creator><creator>Miller, Michael G</creator><creator>Singidi, Harish R</creator><creator>Padilla, Renato C</creator><creator>Besinga, Gary F</creator><creator>Awusie, Roland J</creator><creator>Hoei, Jung Sheng</creator><creator>Muchherla, Kishore Kumar</creator><scope>EVB</scope></search><sort><creationdate>20190207</creationdate><title>MEMORY DEVICES WITH READ LEVEL CALIBRATION</title><author>Alsasua, Gianni S ; Fei, Peng ; Miller, Michael G ; Singidi, Harish R ; Padilla, Renato C ; Besinga, Gary F ; Awusie, Roland J ; Hoei, Jung Sheng ; Muchherla, Kishore Kumar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2019043592A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Alsasua, Gianni S</creatorcontrib><creatorcontrib>Fei, Peng</creatorcontrib><creatorcontrib>Miller, Michael G</creatorcontrib><creatorcontrib>Singidi, Harish R</creatorcontrib><creatorcontrib>Padilla, Renato C</creatorcontrib><creatorcontrib>Besinga, Gary F</creatorcontrib><creatorcontrib>Awusie, Roland J</creatorcontrib><creatorcontrib>Hoei, Jung Sheng</creatorcontrib><creatorcontrib>Muchherla, Kishore Kumar</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Alsasua, Gianni S</au><au>Fei, Peng</au><au>Miller, Michael G</au><au>Singidi, Harish R</au><au>Padilla, Renato C</au><au>Besinga, Gary F</au><au>Awusie, Roland J</au><au>Hoei, Jung Sheng</au><au>Muchherla, Kishore Kumar</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY DEVICES WITH READ LEVEL CALIBRATION</title><date>2019-02-07</date><risdate>2019</risdate><abstract>Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | MEMORY DEVICES WITH READ LEVEL CALIBRATION |
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