MEMORY DEVICES WITH READ LEVEL CALIBRATION

MEMORY DEVICES WITH READ LEVEL CALIBRATION

Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Alsasua, Gianni S, Fei, Peng, Miller, Michael G, Singidi, Harish R, Padilla, Renato C, Besinga, Gary F, Awusie, Roland J, Hoei, Jung Sheng, Muchherla, Kishore Kumar
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.