SCALABLE PROCESSOR-ASSISTED GUEST PHYSICAL ADDRESS TRANSLATION

SCALABLE PROCESSOR-ASSISTED GUEST PHYSICAL ADDRESS TRANSLATION

Examples include a processor including at least one untrusted extended page table (EPT), circuitry to execute a set of instructions of the instruction set architecture (ISA) of the processor to manage at least one secure extended page table (SEPT), and a physical address translation component to tra...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: THIYAGARAJAH, Arumugam, SAHITA, Ravi, HUNTLEY, Barry E, CHAIKIN, Baruch, NEIGER, Gilbert, AHARON, Arie, SHANBHOGUE, Vedvyas, CASPI, Dror
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Examples include a processor including at least one untrusted extended page table (EPT), circuitry to execute a set of instructions of the instruction set architecture (ISA) of the processor to manage at least one secure extended page table (SEPT), and a physical address translation component to translate a guest physical address of a guest physical memory to a host physical address of a host physical memory using one of the at least one untrusted EPT and the at least one SEPT.