INTERFACE FROM NULL CONVENTION LOGIC TO SYNCHRONOUS MEMORY

INTERFACE FROM NULL CONVENTION LOGIC TO SYNCHRONOUS MEMORY

Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a fi...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Cope, Bryan Garnett, Wijayasekara, Vidura Manu, Melton, Ben Wiley
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.