CMOS COMPATIBLE LOW GATE CHARGE HIGH VOLTAGE PMOS

A split gate power transistor includes a laterally configured power PMOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the channel region and a transition region of the substrate. The static plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate.