AGGREGATING CACHE MAINTENANCE INSTRUCTIONS IN PROCESSOR-BASED DEVICES

Aggregating cache maintenance instructions in processor-based devices is disclosed. In this regard, a processor-based device comprises one or more processing elements (PEs), each providing an aggregation circuit configured to detect a first cache maintenance instruction in an instruction stream. The...

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Bibliographische Detailangaben
Hauptverfasser: Stempel, Brian Michael, McAvoy, William James, Speier, Thomas Philip
Format: Patent
Sprache:eng
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Zusammenfassung:Aggregating cache maintenance instructions in processor-based devices is disclosed. In this regard, a processor-based device comprises one or more processing elements (PEs), each providing an aggregation circuit configured to detect a first cache maintenance instruction in an instruction stream. The aggregation circuit then aggregates one or more subsequent, consecutive cache maintenance instructions in the instruction stream with the first cache maintenance instruction until an end condition is detected (e.g., detection of a data synchronization barrier instruction or a cache maintenance instruction targeting a non-consecutive memory address or a different memory page than a previous cache maintenance instruction, and/or detection that an aggregation limit has been exceeded). After detecting the end condition, the aggregation circuit generates a single cache maintenance request representing the aggregated cache maintenance instructions. In this manner, multiple cache maintenance instructions may be represented by and processed as a single request, thus minimizing the impact on system performance.