PROCESSING COMMANDS VIA DEDICATED REGISTER PAIRS FOR EACH THREAD OF A PLURALITY OF THREADS

PROCESSING COMMANDS VIA DEDICATED REGISTER PAIRS FOR EACH THREAD OF A PLURALITY OF THREADS

A hardware acceleration block is configured to process via a dedicated pair of registers, a plurality of commands of each of a plurality of threads received from a compute complex. The hardware acceleration block receives successive commands that are separated by at least an amount of time, from a t...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: RAMALINGAM, Anand S
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A hardware acceleration block is configured to process via a dedicated pair of registers, a plurality of commands of each of a plurality of threads received from a compute complex. The hardware acceleration block receives successive commands that are separated by at least an amount of time, from a thread of the plurality of threads. The amount of time is adequate to process a command from the thread.