VOLTAGE REGULATOR EFFICIENCY-AWARE SYSTEM ENERGY MANAGEMENT

VOLTAGE REGULATOR EFFICIENCY-AWARE SYSTEM ENERGY MANAGEMENT

A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying t...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Dibbad, Vijayakumar A, Prathaban, Satish, Muralidhar, Rajeev D, Seshadri, Harinarayanan
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.