Computer Processor Employing Phases of Operations Contained in Wide Instructions
A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each including a plurality of encoding slots that contain a plurality of different operations. The plurality of encoding slots and the operations contained therein for each wide instruction...
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| Sprache: | eng |
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| Zusammenfassung: | A computer processor employs an instruction processing pipeline that processes a sequence of wide instructions each including a plurality of encoding slots that contain a plurality of different operations. The plurality of encoding slots and the operations contained therein for each wide instruction are statically assigned to different phases of execution belonging to an ordered set of phases of execution. The ordered set of phases of execution can have a predefined order that allows data produced by execution of an operation in an earlier phase of execution to be consumed by execution of at least one other operation in a later phase of execution. |
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