SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

A semiconductor memory device includes a memory cell array having a plurality of memory cell groups, the memory cell groups including a first memory group including first memory cells, and a control circuit configured to execute a first write operation targeting the first memory cells in a first mode in which the control circuit executes at least a first programming operation on the first memory cells followed by a multiple number of first verification operations to verify the first programming operation, and then in a second mode, in which the control circuit executes a second programming operation on the first memory cells followed by a second verification operation to verify the second programming operation. A programming voltage applied during the second programming operation is less than a programming voltage applied during the first programming operation, and is adjusted based on a number of first verification operations.