SYSTEMS AND METHODS FOR CONTROLLING MEMORY ARRAY POWER CONSUMPTION

A memory system has a memory array divided into a plurality of sub-arrays in which each sub-array has a mutually exclusive power domain, task scheduler circuitry coupled to the memory array, and sub-array power control circuitry coupled to the task scheduler circuitry. A method includes selecting, by the task scheduler circuitry, a task for execution, providing a control signal to the sub-array power control circuitry indicative of a set of sub-arrays to power based on the selected task, and setting a power state of each sub-array, by the sub-array control circuitry, in response to the control signal.