MEMORY ARRAY AND METHOD OF FORMING THE SAME

MEMORY ARRAY AND METHOD OF FORMING THE SAME

A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second colu...

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Bibliographische Detailangaben
Hauptverfasser: CHANG, Cheng-Jen, LIN, Geng-Cing, HU, Yu-Hao, CHEN, Yi-Tzu, YANG, Hao-I
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Beschreibung
Zusammenfassung:A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.