Chip scale package

Chip scale package

The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Sprogies, Tobias, Schnitt, Wolfgang
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface.