PROTOCOL FOR MEMORY POWER-MODE CONTROL

In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	Richardson, Wayne S, Ware, Frederick A, Ellis, Wayne F, Kasamsetty, Kishore Ven, Lai, Lawrence, Bansal, Akash
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.