BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES
Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal...
Gespeichert in:
| Hauptverfasser: | , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | CLENDENNING, Scott B KLOSTER, Grant M FRASURE, Kent N MITAN, Martin M GLASSMAN, Timothy E GSTREIN, Florian GRIGGIO, Flavio HOURANI, Rami |
| description | Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2018130707A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2018130707A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2018130707A13</originalsourceid><addsrcrecordid>eNrjZHB28g8J8ffVDQ1QcPP08VHQcAp101Twd1PwdQ1x9FFwc3UMCQ1yDVZw8w9SCHb19XT293MJdQ4B8UKCgAyQJA8Da1piTnEqL5TmZlB2cw1x9tBNLciPTy0uSExOzUstiQ8NNjIwtDA0NjA3MHc0NCZOFQDIFyxl</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES</title><source>esp@cenet</source><creator>CLENDENNING, Scott B ; KLOSTER, Grant M ; FRASURE, Kent N ; MITAN, Martin M ; GLASSMAN, Timothy E ; GSTREIN, Florian ; GRIGGIO, Flavio ; HOURANI, Rami</creator><creatorcontrib>CLENDENNING, Scott B ; KLOSTER, Grant M ; FRASURE, Kent N ; MITAN, Martin M ; GLASSMAN, Timothy E ; GSTREIN, Florian ; GRIGGIO, Flavio ; HOURANI, Rami</creatorcontrib><description>Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180510&DB=EPODOC&CC=US&NR=2018130707A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180510&DB=EPODOC&CC=US&NR=2018130707A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CLENDENNING, Scott B</creatorcontrib><creatorcontrib>KLOSTER, Grant M</creatorcontrib><creatorcontrib>FRASURE, Kent N</creatorcontrib><creatorcontrib>MITAN, Martin M</creatorcontrib><creatorcontrib>GLASSMAN, Timothy E</creatorcontrib><creatorcontrib>GSTREIN, Florian</creatorcontrib><creatorcontrib>GRIGGIO, Flavio</creatorcontrib><creatorcontrib>HOURANI, Rami</creatorcontrib><title>BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES</title><description>Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHB28g8J8ffVDQ1QcPP08VHQcAp101Twd1PwdQ1x9FFwc3UMCQ1yDVZw8w9SCHb19XT293MJdQ4B8UKCgAyQJA8Da1piTnEqL5TmZlB2cw1x9tBNLciPTy0uSExOzUstiQ8NNjIwtDA0NjA3MHc0NCZOFQDIFyxl</recordid><startdate>20180510</startdate><enddate>20180510</enddate><creator>CLENDENNING, Scott B</creator><creator>KLOSTER, Grant M</creator><creator>FRASURE, Kent N</creator><creator>MITAN, Martin M</creator><creator>GLASSMAN, Timothy E</creator><creator>GSTREIN, Florian</creator><creator>GRIGGIO, Flavio</creator><creator>HOURANI, Rami</creator><scope>EVB</scope></search><sort><creationdate>20180510</creationdate><title>BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES</title><author>CLENDENNING, Scott B ; KLOSTER, Grant M ; FRASURE, Kent N ; MITAN, Martin M ; GLASSMAN, Timothy E ; GSTREIN, Florian ; GRIGGIO, Flavio ; HOURANI, Rami</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2018130707A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CLENDENNING, Scott B</creatorcontrib><creatorcontrib>KLOSTER, Grant M</creatorcontrib><creatorcontrib>FRASURE, Kent N</creatorcontrib><creatorcontrib>MITAN, Martin M</creatorcontrib><creatorcontrib>GLASSMAN, Timothy E</creatorcontrib><creatorcontrib>GSTREIN, Florian</creatorcontrib><creatorcontrib>GRIGGIO, Flavio</creatorcontrib><creatorcontrib>HOURANI, Rami</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CLENDENNING, Scott B</au><au>KLOSTER, Grant M</au><au>FRASURE, Kent N</au><au>MITAN, Martin M</au><au>GLASSMAN, Timothy E</au><au>GSTREIN, Florian</au><au>GRIGGIO, Flavio</au><au>HOURANI, Rami</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES</title><date>2018-05-10</date><risdate>2018</risdate><abstract>Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2018130707A1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T01%3A48%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CLENDENNING,%20Scott%20B&rft.date=2018-05-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2018130707A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |