SEQUENCE AND TIMING CONTROL OF WRITING AND REWRITING PIXEL MEMORIES WITH SUBSTANTIALLY LOWER DATA RATE

A Display system driven with binary pulse-width-modulation requires very high data transfer rate to achieve high grayscale. This invention discloses the embodiments of hardware structures and configurations which enable to reduce substantially the data transfer rate using non-sequential order of binary bits, wherein the combination of the sequences of binary bits is selected from the combinations which avoid simultaneous writing of multiple rows. The implementation of this invention substantially reduces the power consumption and the number of connecting pads of display chip