Multi-CPU Device with Tracking of Cache-Line Owner CPU

A processing apparatus includes multiple Central Processing Units (CPUs) and a coherence fabric. Respective ones of the CPUs include respective local cache memories and are configured to perform memory transactions that exchange cache-lines among the local cache memories and a main memory that is shared by the multiple CPUs. The coherence fabric is configured to identify and record in a centralized data structure, per cache-line, an identity of at most a single cache-line-owner CPU among the subset of CPUs that is responsible to commit the cache-line to the main memory; and to serve at least a memory transaction from among the memory transactions, which pertains to a given cache-line among the cache-lines, based on the identity of the cache-line-owner CPU of the cache-line, as recorded in the centralized data structure.