PHASE-LOCKED LOOPS WITH ELECTRICAL OVERSTRESS PROTECTION CIRCUITRY

An integrated circuit with a phase-locked loop (PLL) is provided. The PLL may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. The phase frequency detector may be configured to align or lock a feedback clock signal to a reference clock signal. The control block includes clock loss detection circuits that are used to determine whether the reference clock signal or the feedback clock signal has stopped toggling. In response to detecting a clock loss event for either the reference or the feedback clock signal, the control block may disable the phase frequency detector to place the charge pump in a tristate mode and may apply a predetermined bias voltage to the source follower circuit to help minimize electrical overstress.