INTERFACE SUBSTRATE AND METHOD OF MAKING THE SAME

INTERFACE SUBSTRATE AND METHOD OF MAKING THE SAME

A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable man...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BEZUK Steve Joseph, ADAY Jon Gregory, BUCHAN Nicholas Ian, WE Hong Bok
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.